• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
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    • 专利摘要:
    The synchronous retention latch circuit (CBSR) comprises a first module (M1) adapted to be powered by an interruptible power source (SAI) and a second module (M2) adapted to be powered by a permanent power source ( SAP). The first module (M1) comprises a first latch stage (EV1) and a second latch stage (EV2) configured to store at least one datum (D) in the presence of said interruptible power source (SAI), means for transmission (MT) adapted to be controlled by a second control signal (SC2) and configured to deliver said at least one data item (D) to the second module (M2) before a cut-off of said interruptible power source (AIS), the second module (M2) being configured to keep said at least one datum (D) during said cutoff, and restitution means (MR) adapted to be controlled by a first control signal (SC1) and configured to restore said at least one data (D) at the end of said cut. Only the second control signal (SC2) remains active during the interruption of the interruptible power supply (UPS).
    公开号:FR3056364A1
    申请号:FR1658753
    申请日:2016-09-19
    公开日:2018-03-23
    发明作者:Pascal Urard；Alok Kumar Tripathi
    申请人:STMicroelectronics SA；STMicroelectronics International NV；
    IPC主号:
    专利说明:

    Holder (s): STMICROELECTRONICS SA Public limited company, STMICROELECTRONICS INTERNATIONAL N.V ..
    Extension request (s)
    Agent (s): CASALONGA.
    FR 3 056 364 - A1
    104 / METHOD FOR MANAGING THE OPERATION OF A SYNCHRONOUS LOCKING CIRCUIT WITH ULTRA LOW LEAKAGE CURRENT, AND CORRESPONDING CIRCUIT.
    ©) The synchronous retention flip-flop circuit (CBSR) comprises a first module (M1) adapted to be supplied by an interruptible power source (SAI) and a second module (M2) adapted to be supplied by a power source permanent (SAP). The first module (M1) comprises a first lock stage (EV1) and a second lock stage (EV2) configured to store at least one data item (D) in the presence of said interruptible power source (SAI), means for transmission (MT) adapted to be controlled by a second control signal (SC2) and configured to deliver said at least one datum (D) to the second module (M2) before cutting off said interruptible power source (SAI), the second module (M2) being configured to store said at least one datum (D) during said cut-off, and restitution means (MR) adapted to be controlled by a first control signal (SC1) and configured to restore said at least one given (D) at the end of said cut.
    Only the second control signal (SC2) remains active during the interruption of the interruptible power source (SAI).
    Method for managing the operation of a synchronous flip-flop retention circuit with ultra low leakage current, and corresponding circuit
    Modes of implementation and embodiment of the invention relate to the sequential logic circuits, more particularly the synchronous flip-flop circuits of retention, commonly known to those skilled in the art under the Anglo-Saxon designation "Retention Flip Flop", c that is, configured to be capable of retaining, when a major portion of said synchronous flip-flop circuits are powered down, data stored using a small portion of said permanently powered circuits.
    With a dimension of transistors continuously decreasing in integrated circuits thanks to the advancement of technologies such as CMOS SOI technology below the 100 nm bar, the power consumption linked to static leakage currents becomes more and more significant. in view of the overall consumption of integrated circuits.
    Several techniques such as switching the power source and using transistors having several threshold voltages, commonly known to those skilled in the art under the acronym "MTCMOS" ("Multi-threshold CMOS") are adopted so as to reduce the consumption linked to static leakage currents.
    However, these techniques cannot store data, for example during a power supply cut-out for integrated circuits.
    Under these circumstances, synchronous flip-flop circuits for data retention are generally used in order not only to reduce the consumption of static leakage currents, but also to avoid the loss of stored data.
    However, the use of synchronous flip-flop circuits for data retention generally requires numerous control signals and a non-negligible silicon surface.
    Thus, according to one embodiment and embodiment, it is proposed to offer a technical solution with low complexity and with a small silicon surface to reduce the consumption of leakage currents of a synchronous flip-flop circuit for data retention. .
    According to one aspect, there is proposed a method for managing the operation of a synchronous retention flip-flop circuit comprising a first module adapted to be supplied by an interruptible power source, that is to say adapted to be interrupted, and a second module adapted to be powered by a permanent power source.
    The method comprises storage of at least one data item in the first module in the presence of the interruptible power source, the storage being controlled by a first control signal and an internal clock signal, a delivery of said at least one given to the second module before a cut-off of the interruptible power source, said delivery being controlled by a second control signal, a retention of said at least one data item in the second module during the cut-off, said retention being controlled by the second signal command, and a restitution of said at least one datum in the first module at the end of the cut-off, said restitution being controlled by the first command signal.
    Advantageously, only the second control signal remains active during the interruption of the interruptible power source.
    Such use of a single active control signal, here the second control signal, during the retention of said at least one data makes it possible to reduce the number of control signals during restitution as well as the silicon surface, and consequently to reduce the leakage current consumption thanks to said reduction.
    According to another aspect, a synchronous retention flip-flop circuit is proposed comprising a first module adapted to be supplied by an interruptible power source and a second module adapted to be supplied by a permanent power source.
    The first module comprises first control means configured to deliver a first control signal, a clock stage configured to generate an internal clock signal, a first lock stage adapted to be controlled by the internal clock signal and a second lock stage adapted to be controlled by the first control signal and the internal clock signal, configured to store at least one data item in the presence of said interruptible power source, transmission means adapted to be controlled by a second control signal and configured to deliver said at least one datum to the second module before a cutoff of said interruptible power source, the second module being configured to store said at least one datum during said cutoff, and restitution means adapted to be controlled by the first control signal and configured to output said at least a data.
    The second module includes second control means configured to deliver the second control signal.
    Only the second control signal remains active during the interruption of the interruptible power source.
    According to one embodiment, the first module comprises a first transmission stage adapted to be controlled by the internal clock signal and coupling the second lock stage to the first lock stage, the transmission means comprise a second suitable transmission stage to be controlled by the second control signal and coupled between the second lock stage and the second module, and the restitution means comprise a third transmission stage adapted to be controlled by the first control signal, coupled between the second stage lock and the second module.
    According to another embodiment, the first transmission stage, adapted to be controlled by the internal clock signal, is configured to be in a passing state only when the internal clock signal has a first value, and the second stage lock, adapted to be controlled by the internal clock signal, is configured to store said at least one datum only when the internal clock signal has a second value, complementary to the first value.
    By way of nonlimiting example, the first lock stage may include a first three-state inverter adapted to be controlled by the internal clock signal (SHI). The second latch stage may include a second three-state inverter suitable for being controlled by the first control signal. The second transmission stage may include a second three-state inverter suitable for being controlled by the second control signal. The third transmission stage may include a fourth three-state inverter suitable for being controlled by the first control signal.
    According to yet another embodiment, the second module comprises a third latch stage coupled to the first module, adapted to be controlled by the second control signal and configured to store said at least one datum.
    The third latch stage can for example comprise a fifth three-state inverter suitable for being controlled by the second control signal.
    Advantageously, the second module and the second transmission stage can comprise transistors of the ultra high threshold voltage type.
    The use of such transistors makes it possible to further reduce the static leakage current of the second module adapted to be supplied by the permanent power source so as to reduce the overall energy consumption of said synchronous flip-flop circuit of retention, in particular during the interruption of the interruptible power source.
    According to another aspect, a system is proposed comprising at least one circuit as defined above.
    According to yet another aspect, an electronic device such as a cellular mobile telephone, a tablet or a laptop is proposed, comprising at least one system as defined above.
    Other advantages and characteristics of the invention will appear on examining the detailed description of modes of implementation and embodiments, in no way limiting, and the appended drawings in which:
    - Figures 1 to 3 schematically illustrate modes of implementation and embodiment of the invention.
    FIG. 1 very schematically illustrates an electronic apparatus AE, for example a cellular mobile telephone, comprising a processing system SYS, here for example a system of shift registers, itself comprising a synchronous flip-flop circuit such as for example a synchronous flip-flop circuit called CBSR (“Retention Flip-Flop Circuit” in English).
    Fe synchronous flip-flop circuit CBSR comprises a first module Ml supplied by an interruptible power source SAI, that is to say a power source which can be interrupted, and a second module M2 supplied by a source SAP permanent supply.
    Fe synchronous flip-flop circuit CBSR is configured to store in the first module Ml of the CBSR circuit at least one data item that we want to keep, transfer said at least one data item to the second module M2 of the CBSR circuit prior to cutting the source interruptible power supply SAI so as to reduce the overall consumption of the CBSR circuit, keep said at least one data item in the second module M2 during said cutoff, and restore said data item in the first module Ml after the cutoff of the source SAI interruptible power supply, that is, when the SAI interruptible power source is restored.
    Reference is now made to FIG. 2 to illustrate in more detail an example of the structure of a CBSR synchronous flip-flop circuit according to the invention. For the sake of simplification, the example illustrated is a 1 bit synchronous retention flip-flop circuit.
    The first module M1 is mainly adapted to be controlled by a first control signal SCI supplied by the interruptible power source SAI and a second control signal SC2 supplied by the permanent power source SAP.
    The first module M1 comprises a clock stage configured to deliver an internal clock signal SHI and a complementary internal clock signal SHIC, and an input stage EE comprising here for example a synchronous flip-flop for scanning BAB ("scan flip flop ”intended to receive on these three inputs a data signal SD, a test signal ST and a test command signal SCT.
    The synchronous flip-flop BAB is clocked by the internal clock signal SHI and the complementary internal clock signal SHIC.
    When the internal clock signal SHI is in its low state, the synchronous flip-flop BAB delivers at its output SBAB the data signal SD or the test signal ST according to the value of the test control signal SCT. If the test command signal SCT is in its high state, the test signal ST is selected. Otherwise, the data signal will be delivered to the SBAB output of the BAB synchronous flip-flop.
    When the internal clock signal SHI is in its high state, no signal is delivered by the synchronous flip-flop BAB.
    The first module Ml also includes a first lock stage EV1 and a first transmission stage ET1 coupled in series between the input stage EE and a first output node NSI of the first module Ml.
    The first EV1 latch stage comprises a first latch (“latch” in English) comprising a logic gate of the NOR type (“NOR” in English) PNOU and a first three-state inverter ITE1 coupled head to tail between the SBAB output of the synchronous flip-flop and the SEVI output of the first lock stage.
    The logic gate of the NOR-OR PNOU type comprises a first input coupled to the output SBAB of the synchronous flip-flop BAB, a second input coupled to a complementary reset signal SRC and an output coupled to the output SEVI of the first lock stage EV1.
    The complementary reset signal SRC is generally put in its low state so as to allow the NOR gate or PNOU to function as a conventional inverter. When the complementary reset signal SRC is set to its high state, the first lock stage EV1 delivers a low logic value ("0") at its output SEVI.
    The first three-state inverter ITE1 is adapted to be controlled by the internal clock signal SHI and the complementary internal clock signal SHIC and functions as a conventional inverter when the internal clock signal SHI is in its high state and the SHIC complementary internal clock signal is in its low state. Otherwise, the first three-state inverter ITE1 is in its high impedance state.
    In other words, if the complementary reset signal SRC is in its low state, the first lock stage EV1 functions as a conventional lock when the internal clock signal SHI is in its high state and the internal clock signal complementary SHIC is in its low state. Otherwise, the first EV1 latch stage operates as a conventional inverter.
    If the complementary reset signal SRC is in its high state, a low logic value (“0”) is delivered to the output SEVI of the first stage of latch EV1 regardless of the state of the internal clock signal SHI and of the signal SHIC complementary internal clock.
    The first transmission stage ET1 comprises a first inverter INV1 and a first pair of transmission transistors TT1 coupled in series between the output SEVI of the first latch stage EV1 and the first output node NSI of the first module M1.
    The first pair of transmission transistors TT1 comprises a first PMOS transistor TPI and a first NMOS transistor TN1 coupled in parallel and adapted to be controlled respectively by the complementary internal clock signal SHIC and the internal clock signal SHI.
    The first pair of transmission transistors TT1 is in its on state only when the internal clock signal SHI is in its high state and the complementary internal clock signal SHIC is in its low state.
    Therefore, the first transmission stage ET1 transmits to the first output node NSI data D of the data signal SD or the test signal ST stored in the first latch stage EV1 only when the internal clock signal SHI is in its high state and the complementary internal clock signal SHIC is in its low state.
    The first module M1 also includes a second lock stage EV2 whose output SEV2 is coupled to the first output node NSI. This second EV2 latch stage comprises a second three-state inverter ITE2 coupled between the first output node
    NSI and the EEV2 input of the second EV2 latch stage, and a second pair of the TT2 transmission transistors and a NAND logic gate (“NAND” in English) PNET coupled in series between the first NSI output node and the EEV2 input of the second EV2 lock stage.
    The second three-state inverter ITE2 is adapted to be controlled by a first control signal SCI and a first complementary control signal SCC1 and functions as a conventional inverter when the first control signal SCI is in its high state and the first control signal SCC1 is in its low state.
    The PNET NAND logic gate has a first input coupled to the EEV2 input of the second latch stage EV2, a second input coupled to a reset signal SR, and an output coupled to the second pair of transmission transistors TT2.
    The reset signal SR has a value complemented with that of the complementary reset signal SRC.
    The reset signal SR is generally in its high state so as to allow the NAND gate PNET to function as a conventional inverter. When the reset signal SR is put in its low state, the NAND gate PNET delivers in its output a high logic value ("1").
    The second pair of transmission transistors TT2 comprises a second PMOS transistor TP2 and a second NMOS transistor TN2 coupled in parallel and adapted to be controlled respectively by the internal clock signal SHI and the complementary internal clock signal SHIC.
    The second pair of transmission transistors TT2 is in its on state only when the internal clock signal SHI is in its low state and the complementary internal clock signal SHIC is in its high state. The value of the internal clock signal SHI here is complementary to that used for the first transmission stage ET1 when this first stage is in its on state.
    ίο
    Consequently, if the first control signal SCI and the reset signal SR are in the high state, the first and second latch stages EV1 and EV2 update alternately and successively, at the first output node NSI, the datum D stored in the first and second stages of locks EV1 and EV2, that is to say the data D of the data signal SD or of the test signal ST.
    The first module M1 also includes an output stage ES coupled between the first output node NSI and a second output node NS2. This output stage ES comprises a second inverter INV2 intended to supply a value supplemented by the data stored in the first and second latch stages EV1 and EV2.
    The first module M1 furthermore comprises transmission means MT comprising a second transmission stage ET2 coupled to the output SEV2 of the second lock stage EV2 and restitution means MR comprising a third transmission stage ET3 coupled to the input EEV2 of the second stage of EV2 lock.
    The second transmission stage ET2 comprises a third three-state inverter ITE3 whose input is coupled to the first output node NSI and the output is coupled to the second module M2.
    The second transmission stage ET2 is adapted to be controlled by a second control signal SC2 and a second complementary control signal SCC2, and functions as a conventional inverter when the second control signal SC2 is in the high state and the second signal SCC2 complementary control unit is in the low state.
    The third stage of transmission ET3 comprises a fourth three-state inverter ITE4, the input of which is coupled to the second module M2 and the output of which is coupled to the input EEV2 of the second stage of latch EV2.
    The third transmission stage ET3 is adapted to be controlled by the first control signal SCI and the first complementary control signal SCC1, and functions as a conventional inverter when the first control signal SCI is in the low state and the first signal SCC1 complementary command status is high.
    The second module M2 comprises a third lock stage EV3 whose input EEV3 is coupled to the output of the second transmission stage ET2 and the output SEV3 is coupled to the input of the third transmission stage ET3.
    The third EV3 latch stage has a third INV3 inverter and a fifth ITE5 three-state inverter coupled head-to-tail between the EEV3 input and the SEV3 output of the third EV3 latch stage.
    The fifth three-state inverter ITE5 is adapted to be controlled by the second control signal SC2 and the second complementary control signal SCC2, and functions as a conventional inverter when the second control signal SC2 is in the low state and the second complementary control signal SCC2 is in the high state.
    It should be noted that there is only the second control signal SC2 and the second module M2 which are supplied by the permanent power source SAP. All other signals and the first Ml module are powered by the SAI interruptible power source.
    Furthermore, the second module M2 and the second transmission stage ET2 comprise transistors of the ultra high threshold voltage type so as to obtain very low leakage currents in particular during the interruption of the interruptible power source.
    An ultrahigh threshold voltage type transistor generally has a high doping rate in the channel / substrate region so as to obtain an ultra low leakage current when this transistor is in the off state. The threshold voltage of such a transistor can vary depending on the technology used, for example in a 40nm technology, the threshold voltage of such a transistor can vary between 0.4 and 0.5 V.
    In addition to the means which have just been described, the first and second modules M1 and M2 respectively comprise control means MCM1 and MCM2, for example based on logic circuits, configured to respectively deliver the first control signal SCI and the second signal SC2 control unit.
    Reference is now made to FIG. 3 to schematically illustrate an example of a method for managing the operation of a synchronous flip-flop circuit as defined above.
    By default, the reset signal SR is in the high state and the internal clock signal SHI switches periodically between the high state and the low state.
    In a first step ETP1, the first module M1 stores a datum D to be kept, for example a datum of the data signal SD or of the test signal ST, by putting the first and second control signals SCI and SC2 respectively in the high states and low.
    As a result, the first and second latch stages EV1 and EV2 operate alternately and successively as a function of the internal clock signal SHI so as to store the data D at the first output node NSI. We then obtain the complemented data DC at the second output node NS2 and at the input EEV2 of the second lock stage EV2.
    It should be noted that the second module M2 is isolated from the second latch stage EV2 by the second and third transmission stages ET2 and ET3 because the third and fourth three-state inverters ITE3 and ITE4 are in the high impedance state.
    In a second step ETP2 prior to cutting off the interruptible power supply SAI, the second control signal SC2 is set to the high state so as to make the third three-state inverter ITE3 in the conventional inverter state .
    In this case, the first module M1 transfers the data D, here the complemented data DC, into the second module M2.
    The second control signal SC2 is returned to the low state after the transfer of the data D. Consequently, the third three-state inverter ITE3 returns to the high impedance state and the fifth three-state inverter IT5 functions as an inverter conventional. The third lock stage EV3 is therefore activated so as to keep the data D stored by the first and second lock stages EV1 and EV2.
    In a third step ETP3, the interruptible power source SAI supplying the first module M1 is deactivated for example at the end of the transfer of the data to the second module M2. Consequently, only the second module M2 and the second control signal SC2 remain active during this interruption of the interruptible power supply SAI.
    In a fourth step ETP4 (retention phase), the second control signal SC2 is maintained in the low state during the interruption of the interruptible power source SAI so as to keep the data D in the second module M2.
    As the first module M1 includes most of the transistors of the synchronous flip-flop circuit CBSR, the energy consumption of the circuit CBSR during the cut is greatly reduced.
    In a fifth step ETP5, the first control signal SCI is put in the low state after the interruption of the interruptible power source SAI so as to transfer data D again to the first module M1 via the fourth three-state inverter ITE4.
    Consequently, the first module M1 again receives the data D which had been kept by the second module M2 during the cut-off. In order to make the first lock stage EV1 operational again and to isolate the first and second modules M1 and M2 again, the first control signal SCI is returned to the high state and the second control signal SC2 is maintained in the low state at the end of the data transfer to the first module Ml.
    Thus, a synchronous flip-flop retention circuit is obtained capable of using a single control signal supplied permanently during the retention phase, which advantageously allows a significant reduction in the consumption of said circuit as well as on the silicon surface.
    It should also be noted that the use of a single active control signal 5 during the retention phase is also compatible with a synchronous rocker structure as described in the French patent application filed by the applicants on the same day as the the present patent application and having for title "Method for managing the operation of a synchronous flip-flop circuit of low complexity retention, and corresponding circuit".
    权利要求:
    Claims (10)
    [1" id="c-fr-0001]
    1. Method for managing the operation of a synchronous retention flip-flop circuit (CBSR) comprising a first module (Ml) adapted to be supplied by an interruptible power source (SAI), and a second module (M2) adapted to be powered by a permanent power source (SAP), comprising storage of at least one datum (D) in the first module (Ml) in the presence of the interruptible power source (SAI), the storage being controlled by a first control signal (SCI) and an internal clock signal (SHI), delivery of said at least one datum (D) to the second module (M2) before the interruptible power supply (SAI) is cut off, said delivery being controlled by a second control signal (SC2), a retention of said at least one datum (D) in the second module (M2) during the cut-off, said retention being controlled by the second control signal (SC2), and a restitution of the lad ite at least one datum (D) in the first module (Ml) at the end of the cut-off, said restitution being controlled by the first control signal (SCI), a process in which only the second control signal (SC2) remains active during the interruption of the interruptible power source (SAI).
    [2" id="c-fr-0002]
    2. Synchronous flip-flop circuit (CBSR) comprising a first module (Ml) adapted to be supplied by an interruptible power source (SAI) and a second module (M2) adapted to be supplied by a permanent power source (SAP), the first module (Ml) comprising first control means (MCM1) configured to deliver a first control signal (SCI), a clock stage (EH) configured to generate an internal clock signal (SHI ), a first lock stage (EV1) adapted to be controlled by the internal clock signal (SHI) and a second lock stage (EV2) adapted to be controlled by the first control signal (SCI) and the signal d internal clock (SHI), configured to store at least one datum (D) in the presence of said interruptible power source (SAI), transmission means (MT) adapted to be controlled by a second control signal (SC2) and configured to deliver ladi at least one piece of data (D) at the second module (M2) before a cut-off of said interruptible power source (SAI), the second module (M2) being configured to store said at least one piece of data (D) during said cut-off, and restitution means (MR) adapted to be controlled by the first control signal (SCI) and configured to restore said at least one datum (D) after said cut-off, the second module (M2) comprising second ones control means (MCM2) configured to deliver the second control signal (SC2), only the second control signal (SC2) remaining active during the interruption of the interruptible power source (SAI).
    [3" id="c-fr-0003]
    3. The circuit as claimed in claim 2, in which the first module (Ml) comprises a first transmission stage (ET1) adapted to be controlled by the internal clock signal and coupling the second latch stage (EV2) to the first stage of lock (EV1), the transmission means (MT) comprise a second transmission stage (ET2) adapted to be controlled by the second control signal (SC2) and coupled between the second lock stage (EV2) and the second module ( M2), and the restitution means (MT) comprise a third transmission stage (ET3) adapted to be controlled by the first control signal (SCI), coupled between the second latch stage (EV2) and the second module (M2 ).
    [4" id="c-fr-0004]
    4. The circuit (CBSR) according to claim 3, in which the first transmission stage (ET1), adapted to be controlled by the internal clock signal (SHI), is configured to be in a passing state only when the signal d internal clock (SHI) has a first value, and the second latch stage (EV2), adapted to be controlled by the internal clock signal (SHI), is configured to store said at least one datum (D) only when the internal clock signal (SHI) has a second value, complementary to the first value.
    [5" id="c-fr-0005]
    5. Circuit (CBSR) according to claim 3 or 4, wherein the first latch stage (EV1) comprises a first three-state inverter (ITE1) adapted to be controlled by the internal clock signal (SHI), the second latch stage (EV2) comprises a second three-state inverter (ITE2) adapted to be controlled by the first control signal (SCI), the second transmission stage (ET2) comprises a second three-state inverter (ITE3) adapted to be controlled by the second control signal (SC2), and the third transmission stage (ET3) comprises a fourth three-state inverter (ITE4) adapted to be controlled by the first control signal (SCI).
    [6" id="c-fr-0006]
    6. Circuit (CBSR) according to any one of claims 2 to 5, wherein the second module (M2) comprises a third latch stage (EV3) coupled to the first module (Ml), adapted to be controlled by the second signal control (SC2) and configured to keep said at least one datum (D).
    [7" id="c-fr-0007]
    7. The circuit (CBSR) according to claim 6, in which the third latch stage (EV3) comprises a fifth three-state inverter (ITE5) adapted to be controlled by the second control signal (SC2).
    [8" id="c-fr-0008]
    8. Circuit (CBSR) according to any one of claims 2 to 7, in which the second module (M2) and the second transmission stage (ET2) comprise transistors of the type with ultra high threshold voltage.
    [9" id="c-fr-0009]
    9. System (SYS), comprising at least one circuit (CBSR) according to any one of claims 2 to 8.
    [10" id="c-fr-0010]
    10. Electronic device (AE) such as a cellular cell phone, tablet, or portable computer, comprising at least one system (SYS) according to claim 9.
    1/2
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    FR3056365A1|2016-09-19|2018-03-23|Stmicroelectronics Sa|METHOD FOR MANAGING THE OPERATION OF A SYNCHRONOUS LOW COMPLEXITY RETENTION ROCKER CIRCUIT, AND CORRESPONDING CIRCUIT|
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    2018-03-23| PLSC| Search report ready|Effective date: 20180323 |
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1658753|2016-09-19|
    FR1658753A|FR3056364B1|2016-09-19|2016-09-19|METHOD FOR MANAGING THE OPERATION OF A ULTRA LOW LEAKAGE CURRENT SYNCHRONOUS RETENTION CIRCUIT AND CORRESPONDING CIRCUIT|FR1658753A| FR3056364B1|2016-09-19|2016-09-19|METHOD FOR MANAGING THE OPERATION OF A ULTRA LOW LEAKAGE CURRENT SYNCHRONOUS RETENTION CIRCUIT AND CORRESPONDING CIRCUIT|
    US15/462,494| US10263603B2|2016-09-19|2017-03-17|Method for managing the operation of a synchronous retention flip-flop circuit exhibiting an ultra-low leakage current, and corresponding circuit|
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